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TDA4854 Datasheet(PDF) 18 Page - NXP Semiconductors

Part # TDA4854
Description  I2C-bus autosync deflection controllers for PC/TV monitors
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA4854 Datasheet(HTML) 18 Page - NXP Semiconductors

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1999 Jul 13
18
Philips Semiconductors
Product specification
I2C-bus autosync deflection controllers for
PC/TV monitors
TDA4853; TDA4854
Horizontal oscillator: pins HCAP and HREF
ffr(H)
free-running frequency without
PLL1 action (for testing only)
RHBUF = ∞;
RHREF = 2.4 kΩ;
CHCAP = 10 nF; note 3
30.53
31.45
32.39
kHz
∆f
fr(H)
spread of free-running
frequency (excluding spread of
external components)
−−±3.0
%
TCfr
temperature coefficient of
free-running frequency
−100
0
+100
10−6/K
fH(max)
maximum oscillator frequency
−−
130
kHz
VHREF
voltage at input for reference
current
2.43
2.55
2.68
V
Unlock blanking detection: pin HUNLOCK
Vscan(HUNLOCK)
low level voltage of HUNLOCK
saturation voltage in case
of locked PLL1; internal
sink current = 1 mA
−−
250
mV
Vblank(HUNLOCK)
blanking level of HUNLOCK
external load current = 0
0.9
1
1.1
V
TCblank
temperature coefficient of
Vblank(HUNLOCK)
−−0.9
mV/K
TCsink
temperature coefficient of
Isink(HUNLOCK)
0.15
%/K
Isink(int)
internal sink current
for blanking pulses;
PLL1 locked
1.4
2.0
2.6
mA
IL(max)
maximum external load current
VHUNLOCK =1V
−−−2mA
IL
leakage current
VHUNLOCK = 5 V in case of
unlocked PLL1 and/or
protection active
−−±5
µA
PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF
tW(HSYNC)(max)
maximum width of horizontal
sync pulse (referenced to line
period)
−−
25
%
tlock(HPLL1)
total lock-in time of PLL1
40
80
ms
Ictrl(HPLL1)
control currents
notes 4 and 5
locked mode, level 1
15
−µA
locked mode, level 2
145
−µA
VHBUF
buffered f/v voltage at HBUF
(pin 27)
minimum horizontal
frequency
2.5
V
maximum horizontal
frequency
0.5
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT


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