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ABV0238QCL Datasheet(PDF) 1 Page - Abracon Corporation

Part # ABV0238QCL
Description  750kHz - 800MHz Low Phase Noise Multiplier VCXO
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Manufacturer  ABRACON [Abracon Corporation]
Direct Link  https://abracon.com
Logo ABRACON - Abracon Corporation

ABV0238QCL Datasheet(HTML) 1 Page - Abracon Corporation

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ABV0235/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1
FEATURES
• Selectable 750kHz to 800MHz range.
• Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
• CMOS (ABV0237), PECL (ABV0235 and
ABV0238) or LVDS (ABV0239) output.
• 12 to 25MHz crystal input.
• No external load capacitor or varicap required.
• Output Enable selector.
• Wide pull range (+/-200 ppm)
• Selectable 1/16 to 32x frequency multiplier.
• 3.3V operation.
• Available in 16-Pin (TSSOP or 3x3mm QFN).
DESCRIPTION
The ABV0235 (PECL with inverted OE), ABV0237
(CMOS), ABV0238 (PECL), and ABV0239 (LVDS)
are high performance and low phase noise VCXO IC
chips. They provide phase noise performance as low
as –125dBc at 10kHz offset (at 155MHz), by multi-
plying the input crystal frequency up to 32x. The
wide pull range (+/- 200 ppm) and very low jitter
make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept fun-
damental parallel resonant mode crystals from 12 to
25MHz.
BLOCK DIAGRAM
PIN CONFIGURATION
(Top View)
^: Internal pull-up
*: On 3x3 package, ABV0235/-38 do not have SEL0 available: Pin
10 is VDD, pin 11 is GND. However, ABV0237/-39 have SEL0 (pin
10), and pin11 is VDD. See pin assignment table for details.
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
ABV0238
1
Tri-state
0
Tri-state
ABV0235
ABV0237
ABV0239
1 (Default)
Output enabled
OE input: Logical states defined by PECL levels for ABV0238
Logical states defined by CMOS levels for ABV0237/-39
1
2
3
4
5
6
7
8
VDD
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
A023x
GND
VDD
CLKT
CLKC
12
3
4
12
11
10
9
13
14
15
16
8
7
6
5
SEL3^
XOUT
SEL2^
OE
X+
X-
OE
Q
ABV023x
Vi
n
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
w/
integrated
varicaps


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