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TDA8315 Datasheet(PDF) 9 Page - NXP Semiconductors |
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TDA8315 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 16 page September 1994 9 Philips Semiconductors Preliminary specification Integrated NTSC decoder and sync processor TDA8315T HORIZONTAL PLL; NOTE 12 (FILTER CONNECTED TO PIN 4) fHR holding range PLL −±0.9 ±1.2 kHz fCR catching range PLL note 2 ±0.6 ±0.9 − kHz S/N signal-to-noise ratio of the video input signal at which the time constant is switched − 20 − dB HYS hysteresis at the switching point − 3 − dB HORIZONTAL OUTPUT (PIN 2) VOH HIGH level output voltage IO = 2 mA 2.4 4.0 − V VOL LOW level output voltage IO =2mA − 0.3 0.6 V IO(sink) output sink current −− 2mA IO(source) output source current −− 2mA tW pulse width note 13 − 5.4 −µs td delay time between positive edge of the horizontal output pulse and start of the horizontal sync pulse at the input − 0 −µs BACK PORCH CLAMPING OUTPUT (PIN 10) VOH HIGH level output voltage IO = 2 mA 2.4 4.0 − V VOL LOW level output voltage IO =2mA − 0.3 0.6 V IO(sink) output sink current −− 2mA IO(source) output source current −− 2mA tW pulse width 3.2 3.4 3.6 µs td delay time between start of clamping pulse and start of the start sync pulse 5.2 5.4 5.6 µs VERTICAL OUTPUT (PIN 7); NOTE 14 ffr free-running frequency − 60 − Hz flock locking range 54.6 − 64.5 Hz divider value not locked − 525 − locking range (lines/frame) 488 − 576 VOH HIGH level output voltage IO = 2 mA 2.4 4.0 − V VOL LOW level output voltage IO =2mA − 0.3 0.6 V IO(sink) output sink current −− 2mA IO(source) output source current −− 2mA tW pulse width (6 line periods) − 380 −µs td delay time between start of the vertical sync pulse at the input and the positive edge of the output pulse − 37.5 −µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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