Integrated Silicon Solution, Inc.

1

Rev. A

08/14/07

IS25C32A

IS25C64A

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

32K-BIT/64K-BIT SPI SERIAL

ELECTRICALLY ERASABLE PROM

FEATURES

• Serial Peripheral Interface (SPI) Compatible

— Supports SPI Modes 0 (0,0) and 3 (1,1)

• Wide-voltage Operation

— Vcc = 1.8V to 5.5V

• Low power CMOS

— Active current less than 3.0 mA (2.5V)

— Standby current less than 2.0 µA (2.5V)

• Block Write Protection

— Protect 1/4, 1/2, or Entire Array

• 32 byte page write mode

— Partial page writes allowed

• 10 MHz Clock Rate (5V)

• Self timed write cycles (5 ms Typical)

• High-reliability

— Endurance: 1 million cycles per byte

— Data retention: 100 years

• Industrial and Automotive temperature ranges

• 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP Packages

available

• Lead-free available

AUGUST 2007

The IS25C32A and IS25C64A are electrically erasable

PROM devices that use the Serial Peripheral Interface

(SPI) for communications. The IS25C32A is 32Kbit

(4096 x 8) and the IS25C64A is 64Kbit (8192 x 8). The

IS25C32A/64A EEPROMs are offered in a wide

operating voltage range of 1.8V to 5.5V to be compatible

with most application voltages. ISSI designed the

IS25C32A/64A to be an efficient SPI EEPROM solution.

The devices are packaged in 8-pin PDIP, 8-pin SOIC,

and 8-pin TSSOP.

The functional features of the IS25C32A/64A allow them

to be among the most advanced serial non-volatile

memories available. Each device has a Chip-Select

(

CS) pin, and a 3-wire interface of Serial Data In (SI),

Serial Data Out (SO), and Serial Clock (SCK). While

the 3-wire interface of the IS25C32A/64A provides for

high-speed access, a

HOLD pin allows the memories to

ignore the interface in a suspended state; later the

HOLD pin re-activates communication without re-

initializing the serial sequence. A Status Register

facilitates a flexible write protection mechanism, and a

device-ready bit (

RDY).

DESCRIPTION