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SN65LVCP40RGZG4 Datasheet(PDF) 11 Page - Texas Instruments |
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SN65LVCP40RGZG4 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 23 page www.ti.com JITTER TEST CIRCUIT Characterization Test Board Jitter Test Instrument SN65LVCP40 Pattern Generator D+ D− 20−inch FR4 Coupled Transmission line RX + EQ M U X OUT SMA SMA Coax Coax DC Block DC Block Coax Coax DC Block DC Block SMA SMA <2” 50 Ω TL <2” 50 Ω TL 0 dB Pre-amp 400 mVPP Differential TYPICAL DEVICE BEHAVIOR 0 0 0dB 0 1 3dB 1 0 6dB 1 1 9dB 80 ps/ div Data Eye Input After 30-inch of FR4 Data Eye Output After SN65LVCP40 40 ps/ div SN65LVCP40 SLLS623D – SEPTEMBER 2004 – REVISED FEBRUARY 2006 NOTE: For the Jitter Test, the preemphasis level of the output is set to 0 dB (PREx_x=0) Figure 7. AC Test Circuit – Jitter and Output Rise Time Test Circuit The SN65LVCP40 input equalizer provides 5-dB frequency gain to compensate for frequency loss of a shorter backplane transmission line. For characterization purposes, a 24-inch FR-4 coupled transmission line is used in place of the backplane trace. The 24-inch trace provides roughly 5 dB of attenuation between 375 MHz and 1.875 GHz, representing closely the characteristics of a short backplane trace. The loss tangent of the FR4 in the test board is 0.018 with an effective ε(r) of 3.1. Figure 9. Preemphasis Signal Shape NOTE: 30 Inch Input Trace, dR = 4 Gbps; 27- 1 PRBS Figure 8. Data Input and Output Pattern 11 Submit Documentation Feedback |
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