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U632H64S2K25G1 Datasheet(PDF) 1 Page - Simtek Corporation |
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U632H64S2K25G1 Datasheet(HTML) 1 Page - Simtek Corporation |
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1 / 15 page  U632H64 1 August 15, 2006 STK Control #ML0047 Rev 1.1 PowerStore 8K x 8 nvSRAM Pin Configuration Pin Description Top View 1 VCAP VCCX 28 2 A12 W 27 4 A6 A8 25 5 A5 A9 24 3 A7 HSB 26 6 A4 A11 23 7 A3 G 22 8 A2 A10 21 12 DQ1 DQ5 17 9 A1 E 20 10 A0 DQ7 19 11 DQ0 DQ6 18 13 DQ2 DQ4 16 14 VSS DQ3 15 SOP Signal Name Signal Description A0 - A12 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable VCCX Power Supply Voltage VSS Ground VCAP Capacitor HSB Hardware Controlled Store/Busy The U632H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab- led. The U632H64 is a fast static RAM (25 ns), with a nonvolatile electri- cally erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited num- ber of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place auto- matically upon power down using charge stored in an external 100 μF capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U632H64 combines the high per- formance and ease of use of a fast SRAM with nonvolatile data inte- grity. STORE cycles also may be initia- ted under user control via a soft- ware sequence or via a single pin (HSB). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initia- ted by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Features Description High-performance CMOS non- volatile static RAM 8192 x 8 bits 25 ns Access Time 12 ns Output Enable Access Time ICC = 15 mA at 200 ns Cycle Time Automatic STORE to EEPROM on Power Down using external capacitor Hardware or Software initiated STORE (STORE Cycle Time < 10 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 20 μs) Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature ranges: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD characterization according MIL STD 883C M3015.7-HB (classification see IC Code Numbers) RoHS compliance and Pb- free Package: SOP28 (330 mil) Not Recommended For New Designs |
Similar Part No. - U632H64S2K25G1 |
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Similar Description - U632H64S2K25G1 |
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