5

Rev. B

06/28/02

1

2

3

4

5

6

7

8

9

10

11

12

IS61LV25616L

-10

-12

-15

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max.

Unit

Read Cycle Time

10

—

12

—

15

—

ns

Address Access Time

—

10

—

12

—

15

ns

Output Hold Time

3

—

3

—

3

—

ns

CE Access Time

—

10

—

12

—

15

ns

OE Access Time

—

4

—

5

—

7

ns

OE to High-Z Output

—

4

—

5

0

6

ns

OE to Low-Z Output

0

—

0

—

0

—

ns

CE to High-Z Output

0

4

0

6

0

8

ns

CE to Low-Z Output

3

—

3

—

3

—

ns

LB, UB Access Time

—

4

—

5

—

7

ns

LB, UB to High-Z Output

0

3

0

4

0

5

ns

LB, UB to Low-Z Output

0

—

0

—

0

—

ns

Power Up Time

0

—

0

—

0

—

ns

Power Down Time

—

10

—

12

—

15

ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,

input pulse levels of 0V to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.

Shaded area product in development

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Level

Output Load

See Figures 1 and 2

AC TEST LOADS

Figure 1

Figure 2

319

Ω

5 pF

Including

jig and

scope

353

Ω

OUTPUT

3.3V

319

Ω

30 pF

Including

jig and

scope

353

Ω

OUTPUT

3.3V