UL631H256

11

March 31, 2006

STK Control #ML0057

Rev 1.0

RECALL,SRAM operation cannot commence until

If the UL631H256 is in a WRITE state at the end of

power up RECALL, the SRAM data will be corrupted.

To help avoid this situation, a 10 k

Ω resistor should be

Hardware Protection

The UL631H256 offers hardware protection against

ration will be inhibited.

Low Average Active Power

The UL631H256 has been designed to draw signifi-

cantly less power when E is LOW (chip enabled) but

the cycle time is longer than 45 ns.

When E is HIGH the chip consumes only standby cur-

rent.

The overall average current drawn by the part depends

on the following items:

1. CMOS or TTL input levels

2. the time during which the chip is disabled (E HIGH)

3. the cycle time for accesses (E LOW)

4. the ratio of READs to WRITEs

5. the operating temperature

The information describes the type of component and shall not be considered as assured characteristics. Terms of

delivery and rights to change design reserved.