UL631H256

7

March 31, 2006

STK Control #ML0057

Rev 1.0

Nonvolatile Memory Operations

No.

STORE Cycle Inhibit and

Automatic Power Up RECALL

Symbol

Min.

Max.

Unit

Alt.

IEC

650

μs

Low Voltage Trigger Level

2.4

2.7

V

STORE Cycle Inhibit and Automatic Power Up RECALL

Software Mode Selection

E

W

A13 - A0

(hex)

Mode

I/O

Power

Notes

L

H

0E38

31C7

03E0

3C1F

303F

0FC0

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile STORE

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

l, m

l, m

l, m

l, m

l, m

l, m

L

H

0E38

31C7

03E0

3C1F

303F

0C63

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Read SRAM

Nonvolatile RECALL

Output Data

Output Data

Output Data

Output Data

Output Data

Output High Z

Active

l, m

l, m

l, m

l, m

l, m

l, m

l:

The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL

cycle tables and diagrams for further details.

The following six-address sequence is used for testing purposes and should not be used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C.

m: While there are 15 addresses on the UL631H256, only the lower 14 are used to control software modes.

3.0 V

STORE inhibit

Power Up

RECALL

(24)

t