1998 Nov 03

9

Philips Semiconductors

Product specification

9-bit analog-to-digital converter

for digital video

TDA8761A

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 0.5 ns.

2. Analog input voltages producing code 0 up to and including code 511:

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 511 respectively) are connected to

a) The current flowing into the resistor ladder is

and the full-scale input range at the converter,

to cover code 0 to code 511, is

will be kept reasonably constant from device to device. Consequently variation of the output

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

5.

6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data.

sampling delay time

−

3

−

ns

output hold time

4

−−

ns

output delay time

−

10

13

ns

−

12

15

ns

digital output load

−−

15

pF

3-state output delay times; see Fig.5

enable HIGH

−

5.5

8.5

ns

enable LOW

−

12

15

ns

disable HIGH

−

19

24

ns

disable LOW

−

12

15

ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I

L

V

RT

V

RB

–

R

OB

R

L

R

OT

++

------------------------------------------

=

V

I

R

L

I

L

×

R

L

R

OB

R

L

R

OT

++

------------------------------------------

==

V

RT

(

×

V

–

0.

˙ 852

V

(

RT

V

–

×

=

R

L

R

OB

R

L

R

OT

++

------------------------------------------

GER

V

511

V

0

–

() V

i(p-p)

–

V

i(p-p)

----------------------------------------------------

100

×

=