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DS2155L Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS2155L Datasheet(HTML) 10 Page - Dallas Semiconductor |
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10 / 238 page  DS2155 10 of 238 3. MAIN FEATURES The DS2155 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 SCTs plus many new features. General Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation 8-bit parallel control port, multiplexed or nonmultiplexed, Intel or Motorola IEEE 1149.1 JTAG-Boundary Scan 3.3V supply with 5V tolerant inputs and outputs Pin compatible with DS2156, DS2152/DS2154, and DS21x5Y SCT family Signaling System 7 Support RAI-CI, AIS-CI support 100-pin LQFP (14mm x 14mm) (DS2155L) 100-pin CSBGA (10mm x 10mm) (DS2155G) 3.3V supply with 5V tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG boundary scan Driver source code available from the factory Line Interface Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Fully software configurable Short-haul and long-haul applications Automatic receive sensitivity adjustments Ranges include 0 to -43dB or 0 to -12dB for E1 applications and 0 to -15dB or 0 to -36dB for T1 applications Receive level indication in 2.5dB steps from -42.5dB to -2.5dB Internal receive termination option for 75Ω, 100Ω, and 120Ω lines Internal transmit termination option for 75Ω, 100Ω, and 120Ω lines Monitor application gain settings of 20dB, 26dB, and 32dB G.703 receive synchronization-signal mode Flexible transmit waveform generation T1 DSX-1 line buildouts T1 CSU line buildouts of -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables AIS generation independent of loopbacks Alternating ones and zeros generation Square-wave output Open-drain output option NRZ format option Transmitter power-down Transmitter 50mA short-circuit limiter with current-limit-exceeded indication Transmit open-circuit-detected indication Line interface function can be completely decoupled from the framer/formatter Clock Synthesizer Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from recovered receive clock Jitter Attenuator 32-bit or 128-bit crystal-less jitter attenuator Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats include D4 (SLC-96) and ESF Detailed alarm and status reporting with optional interrupt support Large path and line error counters for: – T1: BPV, CV, CRC6, and framing bit errors – E1: BPV, CV, CRC4, E-bit, and frame alignment errors Timed or manual update modes DS1 idle code generation on a per-channel basis in both transmit and receive paths – User-defined – Digital milliwatt ANSI T1.403-1998 Support RAI-CI detection and generation AIS-CI detection and generation E1ETS 300 011 RAI generation G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-band repeating pattern generators and detectors – Three independent generators and detectors – Patterns from 1 to 8 bits or 16 bits in length RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state |
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