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TDA9151B Datasheet(PDF) 8 Page - NXP Semiconductors |
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TDA9151B Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 36 page July 1994 8 Philips Semiconductors Preliminary specification Programmable deflection controller TDA9151B Table 3 Explanation of control bits shown in Table 2. Table 4 Clock frequency control bit (pin 5; note 1). Note 1. Switching of the prescaler is only allowed when LFSS is LOW. It is highly recommended to hard wire LLCS to ground or VCC. Active switching may damage the output power transistor due to the changing HOUT pulse. This may cause very high currents and large flyback pulses. The permitted combinations of LLC and the prescaler are shown in Table 5. Table 5 Line duration with prescaler. Note 1. Combination not allowed. CONTROL BITS DESCRIPTION LFSS line frame start/stop DINT de-interlace BLDS bleeder mode selection GBS guard band selection VAP polarity of VA edge detection FBL flyback slicing level WS wait state on/off MS mode select CSU clamping suppression mode PRD protection/detection mode DIP de-interlace phase CPR compression on/off VPR vertical power reduction mode CONTROL BIT LOGIC FUNCTION LLCS 0 prescaler on: the internal clock frequency fclk = 1⁄2fLLC 1 prescaler off (default by internal pull-up resistor): the internal clock frequency fclk =fLLC LLC (MHz) ON ( µs) OFF ( µs) 6.75 note 1 64 13.5 64 32 27 32 note 1 |
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