HRF-AT4521

Preliminary

________________________________________________________________________________________________________

Web Site:

www.mysoiservices.com

Honeywell

Email:

mysoiservices@honeywell.com

Solid State Electronics Center

12001 State Highway 55

2002 4521W

Published June 2002

Page 1

Plymouth, Minnesota 55441-4799

1-800-323-8295

31.0 dB, DC-4GHz, 5 Bit

Serial Digital Attenuator

Features

•

Very Low DC Power Consumption

•

Attenuation In Steps From 1 dB To 31 dB

•

Single Or Dual Power Supply Voltages

•

Serial Data Interface

•

50 Ohm Compatible Impedance

•

Space Saving LPCC

Product Description

The

Honeywell

HRF-AT4521

is

a

5-bit

digital

attenuator

that

is

ideal

for

use

in

broadband

communication

system

applications

that

require

accuracy, speed and low power consumption. The

HRF-AT4521

is

manufactured

with

Honeywell's

patented

Silicon

On

Insulator

(SOI)

CMOS

manufacturing

technology,

which

provides

the

performance

of

GaAs

with

the

economy

and

integration capabilities of conventional CMOS.

RF Electrical Specifications @ + 25

Parameter

Test Condition

Frequency

Minimum

Typical

Maximum

Units

Insertion Loss

DC – 0.5 GHz

2.0 GHz

3.0 GHz

4.0 GHz

1.8

2.8

--

--

dB

dB

dB

dB

1dB Compression

VSS = 0V, Input Power

DC – 2.0 GHz

24

dBm

1dB Compression

VSS = - VDD, Input Power

DC – 2.0 GHz

29

dBm

Input IP3

VSS = 0V Two-tone inputs

Up To +5 dBm @ 0 dBm

Attenuation

DC – 2.0 GHz

38

dBm

Input IP3

Two-tone inputs Up To + 5

dBm @ 0 dBm Attenuation

DC – 2.0 GHz

>38

dBm

Return Loss*

Any Combination of Bits

DC - 4.0 GHz

11

dB

Attenuation Accuracy

All attenuation states

All attenuation states

All attenuation states

All attenuation states

DC – 1.0 GHz

2.0 GHz

3.0 GHz

4.0 GHz

+/-(0.3 + 3% of programmed IL)

+/-(0.3 + 3% of programmed IL)

+/-(0.4 + 4% of programmed IL)

+/-(0.5 + 6% of programmed IL)

dB

dB

dB

dB

Trise, Tfall*

Ton, Toff (Tpd)

Transients

10% To 90%

50% Cntl To 90%/10%RF

In-Band

TBD

nS

nS

mV

T clock Period (Tprd)*

T high / T low = ½ minimum clock period

50

nS

T data set up (Tsup)*

Set up to rising edge of clock

5

nS

T data hold (Thld)*

Data hold after rising edge of clock

2

nS

T latch set up (Tlsup)*

Data set up to falling edge of OE

5

nS

0.01uF Decoupling Capacitors Required On Power Supply Rails.

*By design

HRF-AT4521 in LPCC™ Package