M36W0R6050T1, M36W0R6050B1

Signal descriptions

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2

Signal descriptions

See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals

connected to this device.

2.1

Address inputs (A0-A21)

Addresses A0-A21 are common inputs for the Flash memory and PSRAM components,

whereas A21 is an address input for the Flash memory component only. The Address Inputs

select the cells in the memory array to access during Bus Read operations. During Bus

Write operations they control the commands sent to the Command Interface of the Flash

memory Program/Erase Controller, and they select the cells to access in the PSRAM.

2.2

Data inputs/outputs (DQ0-DQ15)

For the Flash memory, the Data I/O outputs the data stored at the selected address during a

Bus Read operation or inputs a command or the data to be programmed during a Write Bus

operation.

For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper

part of the selected address during a Write or Read operation, when Upper Byte Enable

Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the

Low.

2.3

The Chip Enable inputs activate the memory control logics, input buffers, decoders and

high impedance and the power consumption is reduced to the standby level.

2.4

The Output Enable pins control data outputs during Flash memory Bus Read operations.

2.5

The Write Enable controls the Bus Write operation of the Flash memories’ Command

Interface. The data and address inputs are latched on the rising edge of Chip Enable or

Write Enable whichever occurs first.