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9301-01 Datasheet(PDF) 4 Page - Peregrine Semiconductor Corp. |
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9301-01 Datasheet(HTML) 4 Page - Peregrine Semiconductor Corp. |
4 / 7 page Product Specification PE9301 Page 4 of 7 ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0039-02 │ UltraCMOS™ RFIC Solutions Evaluation Kit Operation Figure 6. Evaluation Board Layout Figure 7. Evaluation Board Schematic Peregrine specification 102/0062 Peregrine specification 101/0034 The Ceramic SOIC Prescaler Evaluation Board was designed to help customers evaluate the PE9301 divide-by-2 prescaler. On this board, the device input (pin 2) is connected to the SMA connector J1 through a 50 Ω transmission line. A series capacitor (C3) provides the necessary DC block for the device input. A value of 1000 pF was used for the evaluation board; other applications may require a different value. It is also possible to place a 0 Ω resistor in this location for very low frequency applications. The device output (pin 7) is connected to SMA connector J3 through a 50 Ω transmission line. A series capacitor (C1) provides the necessary DC block for the device output. This capacitor value must be chosen to have a low impedance at the desired output frequency of the device. A value of 1000 pF was chosen for the evaluation board. The board is constructed of a two-layer FR4 material with a total thickness of 0.031”. The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030”, trace gaps of 0.0061”, dielectric thickness of 0.028”, metal thickness of 0.0014”, and ε r of 4.6. Note that the predominate mode of these transmission lines is coplanar waveguide. J2 provides DC power to the device via pin 1. Two decoupling capacitors (C2=100 pF, C10=1000 pF) are included on this trace. It is the responsibility of the customer to determine proper supply decoupling for their design application. |
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