Product Specification

PE9704

Page 3 of 10

Document No. 70-0083-03

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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

Table 1. Pin Descriptions (continued)

17

GND

Both

Ground

18

CLOCK

Serial

Input

Clock input. Data is clocked serially into either the 20-bit primary register (E_WR

“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of

CLOCK.

Direct

Input

M Counter bit6

19

Direct

Input

M Counter bit7

20

Direct

Input

M Counter bit8 (MSB)

21

Direct

Input

A Counter bit0

22

Both

Input

23

Both

(Note 1)

Same as pin 1

24

E_WR

Serial

Input

Enhancement register write enable. While E_WR is “high”, DATA can be serially

clocked into the enhancement register on the rising edge of CLOCK.

Direct

Input

A Counter bit1.

25

Direct

Input

A Counter bit2

26

Direct

Input

A Counter bit3 (MSB)

27

Both

Input

RF prescaler input from the VCO. 3.0 GHz maximum frequency.

28

GND

Both

Ground.

29

GND

Both

Ground.

30

N/C

No connect.

31

Both

(Note 1)

Same as pin 1

32

Serial

Output

Data Out. The Main Counter output, R Counter output, or dual modulus prescaler

33

Both

(Note 1)

Same as pin 1

34

N/C

No connect.

35

GND

Both

Ground.

36

PD_

D

Both

Output

PD_

D pulses down when f

37

PD_

U

Both

PD_

U pulses down when f

38

Both

(Note 1)

Same as pin 1

39

Both

Output

Logical “NAND” of PD_

U and PD_D, passed through an on-chip, 2 kΩ series

inverting amplifier used for driving LD.

40

GND

Both

Ground

41

GND

Both

Ground

42

Both

Input

Reference frequency input

43

ENH

Both

Output, OD

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

44

LD

Serial

Output

locked, LD is high impedance; otherwise LD is a logic low (“0”).

Note 1:

Note 2:

All digital input pins have 70 k

Ω pull-down resistors to ground.

Pin No.

Pin Name

Interface Mode

Type

Description