AN231E04 Datasheet – Dynamically Reconfigurable dpASP
DS231000-U001d
- 9 -
1.4.8
RAM Transfer – Trigger and Arm
These digital inputs do not have dedicated pins, a connection exists within the dpASP, an external signal can be routed to
either of these virtual pins from a type2 I/O cell (I/O cells 5, 6 and 7. Pins 15,16,17,18,19 or 20).
The purpose of these virtual pins is to extend optional asynchronous timing control of the dpASP configuration to the user.
Parameter
Symbol
Min
Typ
Max
Unit
Comment
Input Voltage Low
Vil
0
30
%
% of DVDD
Input Voltage High
Vih
70
100
%
% of DVDD
Minimum pulse width
connected to where
TPW
setup time
5
-
-
ns
Time to register the event
internally.
Pulse-Pulse edge delay
TPT-T
setup time
10
-
-
ns
Delay between pre-trigger and
trigger. Need not be observed if
pre-trigger is not used, is set at
the end of configuration
automatically.
Execute delay
TEXDLY
0
10
20
ns
Delay from trigger rising edge to
internal execute event.
Execute minimum width
TMinEW
1 ALCK
-
2 ACLK
-
Duration of execute pulse
guaranteed 1 ACLK period. Can
be as long as 2 periods
depending on relative phases.
Pre-trigger reset.
TPTR
10
-
-
ns
Pre-trigger circuit is reset ready to
accept another pre-trigger.
Pre-trigger
Trigger
ACLK
T
PW
T
PW
T
PT-T
T
MinEW
T
EXDLY
Internal
RAM
execute
T
PTR
edge (n)
edge (n+1)
AnadigmDesigner2 options, (these are set using the software tool AnadigmDesigner2)
RAM Transfer Trigger = Automatic :
RAM transfer happens automatically immediately after the “end” byte of a configuration bit stream. Timing control is entirely inside the
AN231E04 device and not visible to a user.
RAM Transfer Trigger = Event driven.
RAM Trigger = Off.
no pre-trigger used. The “end” byte of configuration bit stream arms the RAM transfer and the user signal then acts
as the trigger.
Arm Trigger = On
External Signal Allowed = Trigger. This setting allows the external signal connected to be the trigger,
Arming must be from an internal signal.
External Signal Allowed = Arm. This setting allows the external signal connected to be the arming signal,
Trigger be from an internal signal.
RAM Transfer Trigger = Clock synch
RAM transfer happens automatically immediately following the first occurrence of all internal clocks being scyncronous. Timing control is
entirely inside the AN231E04 device and not visible to a user.
HINT:
The RAM transfer timings above are for the trigger block hardware - The Trigger and Arm signals can come from many
sources, propagation delays to the trigger block inputs will vary depending on the source and routing of the signals to this block.
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