COP87L88KGV-XE datasheet(11/42 Pages) NSC

Part #	COP87L88KGV-XE

Description	8-Bit One-Time Programmable (OTP) Microcontroller with UART and Three Multi-Function Timers

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Manufacturer	NSC [National Semiconductor (TI)]

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Control Registers

CNTRL Register (Address X 00EE)

The Timer1 (T1) and MICROWIREPLUS control register

contains the following bits

SL1

SL0 Select the MICROWIREPLUS clock divide

by (00 e 2 01 e 4 1x e 8)

IEDG

External interrupt edge polarity select

(0 e Rising edge 1 e Falling edge)

MSEL

Selects G5 and G4 as MICROWIREPLUS

signals SK and SO respectively

T1C0

Timer T1 StartStop control in timer

modes 1 and 2

Timer T1 Underflow Interrupt Pending Flag in

timer mode 3

T1C1

Timer T1 mode control bit

T1C2

Timer T1 mode control bit

T1C3

Timer T1 mode control bit

T1C3 T1C2 T1C1 T1C0 MSEL IEDG

SL1

SL0

Bit 7

Bit 0

PSW Register (Address X 00EF)

The PSW register contains the following select bits

GIE

Global interrupt enable (enables interrupts)

EXEN

Enable external interrupt

BUSY

MICROWIREPLUS busy shifting flag

EXPND

External interrupt pending

T1ENA

Timer T1 Interrupt Enable for Timer Underflow

or T1A Input capture edge

T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA

in mode 1 T1 Underflow in Mode 2 T1A cap-

ture edge in mode 3)

C

Carry Flag

HC

Half Carry Flag

HC

C T1PNDA T1ENA EXPND BUSY EXEN GIE

Bit 7

Bit 0

The Half-Carry bit is also affected by all the instructions that

affect the Carry flag The SC (Set Carry) and RC (Reset

Carry) instructions will respectively set or clear both the car-

ry flags In addition to the SC and RC instructions ADC

SUBC RRC and RLC instructions affect the carry and Half

Carry flags

ICNTRL Register (Address X 00E8)

The ICNTRL register contains the following bits

T1ENB

Timer T1 Interrupt Enable for T1B Input capture

edge

T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-

ture edge

m

WEN

Enable MICROWIREPLUS interrupt

m

WPND MICROWIREPLUS interrupt pending

T0EN

Timer T0 Interrupt Enable (Bit 12 toggle)

T0PND

Timer T0 Interrupt pending

LPEN

L Port Interrupt Enable (Multi-Input WakeupIn-

terrupt)

Bit 7 could be used as a flag

Unused LPEN T0PND T0EN mWPND mWEN T1PNDB T1ENB

Bit 7

Bit 0

T2CNTRL Register (Address X 00C6)

The T2CNTRL register contains the following bits

T2ENB

Timer T2 Interrupt Enable for T2B Input capture

edge

T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-

ture edge

T2ENA

Timer T2 Interrupt Enable for Timer Underflow

or T2A Input capture edge

T2PNDA Timer T2 Interrupt Pending Flag (Autoreload RA

in mode 1 T2 Underflow in mode 2 T2A cap-

ture edge in mode 3)

T2C0

Timer T2 StartStop control in timer modes 1

and 2 Timer T2 Underflow Interrupt Pending

Flag in timer mode 3

T2C1

Timer T2 mode control bit

T2C2

Timer T2 mode control bit

T2C3

Timer T2 mode control bit

T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB

Bit 7

Bit 0

T3CNTRL Register (Address X 00B6)

The T3CNTRL register contains the following bits

T3ENB

Timer T3 Interrupt Enable for T3B Input capture

edge

T3PNDB Timer T3 Interrupt Pending Flag for T3B cap-

ture edge

T3ENA

Timer T3 Interrupt Enable for Timer Underflow

or T3A Input capture edge

T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA

in mode 1 T3 Underflow in mode 2 T3A cap-

ture edge in mode 3)

T3C0

Timer T3 StartStop control in timer modes 1

and 2

Timer T3 Underflow Interrupt Pending Flag in

timer mode 3

T3C1

Timer T3 mode control bit

T3C2

Timer T3 mode control bit

T3C3

Timer T3 mode control bit

T3C3

T3C2

T3C1

T3C0 T3PNDA T3ENA T3PNDB T3ENB

Bit 7

Bit 0

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COP87L88KGV-XE Datasheet(PDF) 11 Page - National Semiconductor (TI)

COP87L88KGV-XE Datasheet(HTML) 11 Page - National Semiconductor (TI)

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