6

HV758

Name

Function

V

DD

Positive internal voltage supply (+10V).

V

SS

Power supply return (0V).

V

LL

Logic Hi voltage reference input (+3.3V).

G

REF

Logic Low reference, logic ground (0V).

V

SUB

Substrate of the IC, all V

RGND

Bleed resistors common return ground.

V

PP

Positive high voltage power supply (+90V).

V

NN

Negative high voltage power supply (-90V).

V

PF

P-FET drive floating power supply, (V

V

NF

N-FET drive floating power supply, (V

TXP1

Output P-FET drain (open drain output) for channel 1.

TXN1

Output N-FET drain (open drain output) for channel 1.

TXP2

Output P-FET drain (open drain output) for channel 2.

TXN2

Output N-FET drain (open drain output) for channel 2.

TXP3

Output P-FET drain (open drain output) for channel 3.

TXN3

Output N-FET drain (open drain output) for channel 3.

TXP4

Output P-FET drain (open drain output) for channel 4.

TXN4

Output N-FET drain (open drain output) for channel 4.

PIN1

Input logic control of high voltage output P-FET of channel 1, Hi=on, Low=off.

NIN1

Input logic control of high voltage output N-FET of channel 1, Hi=on, Low=off.

PIN2

Input logic control of high voltage output P-FET of channel 2, Hi=on, Low=off.

NIN2

Input logic control of high voltage output N-FET of channel 2, Hi=on, Low=off.

PIN3

Input logic control of high voltage output P-FET of channel 3, Hi=on, Low=off.

NIN3

Input logic control of high voltage output N-FET of channel 3, Hi=on, Low=off.

PIN4

Input logic control of high voltage output P-FET of channel 4, Hi=on, Low=off.

NIN4

Input logic control of high voltage output N-FET of channel 4, Hi=on, Low=off.

EN

Chip power enable Hi=on, Low=off.

MC0, MC1

Output current mode control pins, see Drive Mode Control Table.

OTP

Over temperature protection output, open N-FET drain, active low if IC temperature >110°C.

Ball Description

A1 Corner

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AV

PF

V

PP

V

PP

V

NN

V

NN

V

NF

TXN4

TXN4

BV

PF

V

PP

V

PP

V

NN

V

NN

V

NF

TXP4

TXP4

CV

DD

V

SUB

PIN4

NIN4

MC0

V

SUB

TXN3

TXN3

DV

SS

OTP

PIN3

NIN3

MC1

RGND

TXP3

TXP3

EV

SS

V

LL

PIN2

NIN2

EN

RGND

TXN2

TXN2

FV

DD

V

SUB

PIN1

NIN1

G

REF

V

SUB

TXP2

TXP2

GV

PF

V

PP

V

PP

V

NN

V

NN

V

NF

TXN1

TXN1

HV

PF

V

PP

V

PP

V

NN

V

NN

V

NF

TXP1

TXP1

Ball Configuration