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UAA2077TS Datasheet(PDF) 3 Page - NXP Semiconductors |
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UAA2077TS Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 2000 Apr 17 3 Philips Semiconductors Preliminary specification 2 GHz image rejecting front-end UAA2077TS BLOCK DIAGRAM handbook, full pagewidth FCA012 14 11 LOGND 135 ° 135 ° 16 QUADRATURE PHASE SHIFTER IF COMBINER 13 VCCLO LOCAL OSCILLATOR SECTION RECEIVE SECTION 1 6 LNAGND 2, 5, 8 n.c. 9 GND 10 RXON 7 SXON 4 RFINB 3 RFINA LNA 12 LOINB LOINA × 45 ° 45 ° × 15 VCCLNA IFA IFB UAA2077TS Fig.1 Block diagram. PINNING SYMBOL PIN DESCRIPTION VCCLNA 1 supply voltage for receive section (LNA and IF parts) n.c. 2 not connected RFINA 3 RF input A (balanced) RFINB 4 RF input B (balanced) n.c. 5 not connected LNAGND 6 ground for receive section (LNA and IF parts) SXON 7 SX mode enable input (see Table 1) n.c. 8 not connected GND 9 ground RXON 10 RX mode enable input (see Table 1) LOINB 11 LO input B (balanced) LOINA 12 LO input A (balanced) VCCLO 13 supply voltage for LO section LOGND 14 ground for LO section IFA 15 IF output A (balanced) IFB 16 IF output B (balanced) handbook, halfpage UAA2077TS FCA011 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCCLNA n.c. RFINA RFINB n.c. LNAGND SXON n.c. GND RXON LOINB LOINA VCCLO LOGND IFA IFB Fig.2 Pin configuration. |
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