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UCB1500 Datasheet(PDF) 8 Page - NXP Semiconductors |
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UCB1500 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 58 page Philips Semiconductors UCB1500 PCI to AC97 bridge/host controller Objective specification Rev. 01 — 4 February 2000 8 of 58 9397 750 06854 © Philips Electronics N.V. 2000. All rights reserved. [07-06]: Status Register [08]: Revision ID (read only): Current revision of chip = 1. [0B-09]: Class Code Register (read only): Value = 070300h for simple communication controller, generic modem. Programmable through EEPROM interface or register 47-45h. [0C]: Cache Line Size (read only): Always 0; no cache supported. [0D]: Latency Timer [0E]: Header Type (read only): If multifunction device, value is 80h otherwise 00h. Table 6: Status Register bit description Bit Description 15 PERR detected Set to ‘1’ whenever parity error is detected. Write ‘1’ to clear. 14 SERR asserted Set to ‘1’ if UCB1500 asserted SERR. Write ‘1' to clear. 13 Received master abort If set, UCB1500 has received master abort during its slave operation. Write ‘1’ to clear. 12 Received target abort If set, UCB1500 has received target abort during its master operation. Write `1' to clear 11(r) Target abort Always ‘0’; UCB1500 never signals target abort. 10-9(r) Timing Always 01b; wait state during slave access to UCB1500. 8 PERR reported Not implemented, always 0. 7(r) Fast back-to-back capable Always ‘1’; NO wait state between PCI cycles. 6(r) User Definable features Always ‘0’; device does not support user definable features. 5(r) 66 MHz capable bit Always ‘0’; device is 33 MHz device only. 4(r) Capabilities bit (read only) Always ‘1’; capabilities present. 3-0 Reserved. Table 7: Latency Timer register bit description Bit Description 7-4 Latency Timer Bits 7-4 of the latency timer, in units of PCI clocks * 16. 3-0(r) Latency Timer These bits are read only and are always 0000b, giving timer granularity of 16 PCI clocks. |
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