ICS889872

DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

PRELIMINARY

IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

2

ICS889872AK REV. A AUGUST 22, 2007

Table 1. Pin Descriptions

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1, 2

QB0, nQB0

Output

Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be

terminated with 100W across the pin (QB0/nQB0).

LVDS interface levels.

3, 4

QB1, nQB1

Output

Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be

terminated with 100W across the pin (QB1nQB1).

LVDS interface levels.

5, 6

QA, nQA

Output

Differential undivided output pair. LVDS interface levels.

7, 14

Power

Power supply pins.

8

nRESET/

nDISABLE

Input

Pullup

Output reset and enable/disable pin. When LOW, resets the divider select,

and align Bank A and Bank B edges. In addition, when LOW, Bank A and

Includes a 37k

9

nIN

Input

Inverting differential LVPECL clock input. RT = 50

10

Output

(approx.). Maximum sink/source current is 0.5mA.

11

Input

Termination input. Leave pin floating.

12

IN

Input

Non-inverting LVPECL differential clock input.

RT = 50

13

GND

Power

Power supply ground.

15, 16

S1, S0

Input

Pullup

Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.

Input threshold is VDD/2. 37kW pullup resistor.

LVCMOS/LVTTL interface levels.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Pullup Resistor

37

k

Ω