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M38036FC-XXXWG Datasheet(PDF) 10 Page - Renesas Technology Corp |
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M38036FC-XXXWG Datasheet(HTML) 10 Page - Renesas Technology Corp |
10 / 119 page Rev.1.00 Apr 2, 2007 Page 10 of 117 REJ03B0212-0100 3803 Group (Spec.L) Fig 8. Register push and pop at interrupt generation and subroutine call Interrupt request(1) M(S) ←(PCH) (S) ←(S) − 1 M(S) ←(PCL) ( S) ←(S) − 1 Execute RTS Subroutine (S) ←(S) + 1 (PCL) ←M(S) (S) ←(S) + 1 (PCH) ←M(S) M(S) ←(PCH) (S) ←(S) − 1 M(S) ←(PCL) (S) ←(S) − 1 M(S) ←(PS) (S) ←(S) − 1 Interrupt Service Routine (S) ←(S) + 1 (PS) ←M(S) (S) ←(S) + 1 (PCL) ←M(S) (S) ←(S) + 1 (PCH) ←M(S) Execute JSR Execute RTI Push Return Address on Stack Push Contents of Processor Status Register on Stack I Flag is Set from “0” to “1” Fetch the Jump Vector POP Contents of Processor Status Register from Stack POP Return Address from Stack POP Return Address from Stack Push Return Address on Stack Note 1 : Condition for acceptance of an interrupt → Interrupt enable flag is “1” Interrupt disable flag is “0” On-going Routine Table 4 Push and pop instructions of accumulator or processor status register Push instruction to stack Pop instruction from stack Accumulator PHA PLA Processor status register PHP PLP |
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