AD9627BCPZ-105 datasheet(10/40 Pages) AD

Part #	AD9627BCPZ-105

Description	12-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

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Manufacturer	AD [Analog Devices]

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AD9627

Preliminary Technical Data

Rev. PrA | Page 10 of 40

Pin No.

Mnemonic

Type

Function

ADC INPUTS

37

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

38

VIN-A

Input

Differential Analog Input Pin (−) for Channel A.

44

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

43

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

39

VREF

I/O

Voltage Reference Input/Output.

40

SENSE

Input

Voltage Reference Mode Select (See Table x for details)

42

RBIAS

Input

External Reference Bias Resistor

41

CML

Output

Common Mode Level Bias Output for Analog Inputs

49

CLK+

Input

ADC Master Clock – True (ADC Clock can be driven using single ended CMOS – See

Figure x.x for recommended connection)

50

CLK-

Input

ADC Master Clock - Complement (ADC Clock can be driven using single ended

CMOS – See Figure x.x for recommended connection)

ADC Fast Detect Outputs

29

FD0A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

30

FD1A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

31

FD2A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

32

FD3A

Output

Channel A Fast Detect Indicator (See Table x for full detials)

53

FD0B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

54

FD1B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

55

FD2B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

56

FD3B

Output

Channel B Fast Detect Indicator (See Table x for full detials)

Digital INPUTS

52

SYNC

Input

Digital Synchronization Pin(Slave Mode Only)

Digital OUTPUTS

14, 15, 16,

17, 18, 19,

22, 23, 25,

26, 27, 28

D0A-D11A

Output

Channel A CMOS output data

60, 61, 62,

63, 2, 3, 4,

5, 6, 7, 8, 9

D0B-D11B

Output

Channel B CMOS output data

11

DCOA

Output

Channel A Data Clock Output

10

DCOB

Output

Channel B Data Clock Output

SPI CONTROL

48

SCLK/DFS

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode

47

SDIO/DCS

I/O

SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode

51

CSB

Input

SPI Chip Select (Active Low)

Serial Port

33

SMI SDO/OEB

I/O

Signal monitor Serial Data Output/Output Enable Input (Active Low) in External Pin

Mode

35

SMI SDFS

Output

Signal monitor Serial Data Frame Sync

34

SMI SCLK/PDWN

I/O

Signal monitor Serial Clock Output/Power Down Input in External Pin Mode

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AD9627BCPZ-105 Datasheet(PDF) 10 Page - Analog Devices

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