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IDT7164LS Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT7164LS Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 11 page  6 IDT7164S/L CMOS Static RAM 64K (8K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (con't.) (VCC= 5.0V ± 10%, Military Temperature Ranges) NOTES: 1. Both chip selects must be active for the device to be selected. 2. This parameter is guaranteed by device characterization, but is not production tested. Symbol Parameter 7164S45 7164L45 7164S55 7164L55 7164S70 7164L70 7164S85/100 7164L85/100 Unit Min. Max. Min. Max. Min. Max. Min. Max. Read Cycle tRC Read Cycle Time 45 ____ 55 ____ 70 ____ 85/100 ____ ns tAA Address Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS1(1) Chip Select-1 Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tACS2(1) Chip Select-2 Access Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns tCLZ1,2(2) Chip Select-1, 2 to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ ns tOE Output Enable to Output Valid ____ 25 ____ 30 ____ 35 ____ 40 ns tOLZ(2) Output Enab le to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tCHZ1,2(2) Chip Select-1,2 to Output in High-Z ____ 20 ____ 25 ____ 30 ____ 35 ns tOHZ(2) Output Disab le to Output in High-Z ____ 20 ____ 25 ____ 30 ____ 35 ns tOH Output Hold from Address Change 5 ____ 5 ____ 5 ____ 5 ____ ns tPU(2) Chip Sele ct to Power Up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tPD(2) Chip Deselect to Power Down Time ____ 45 ____ 55 ____ 70 ____ 85/100 ns Write Cycle tWC Write Cycle Time 45 ____ 55 ____ 70 ____ 85/100 ____ ns tCW1,2 Chip Select to End-of-Write 33 ____ 50 ____ 60 ____ 75 ____ ns tAW Address Valid to End-of-Write 33 ____ 50 ____ 60 ____ 75 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 25 ____ 50 ____ 60 ____ 75 ____ ns tWR1 Write Recovery Time ( CS1, WE)0 ____ 0 ____ 0 ____ 0 ____ ns tWR2 Write Recovery Time (CS2)5 ____ 5 ____ 5 ____ 5 ____ ns tWHZ(2) Write Enab le to Output in High-Z ____ 18 ____ 25 ____ 30 ____ 35 ns tDW Data to Write Time Overlap 20 ____ 25 ____ 30 ____ 35 ____ ns tDH1 Data Hold from Write Time ( CS1, WE)0 ____ 0 ____ 0 ____ 0 ____ ns tDH2 Data Hold from Write Time (CS2)5 ____ 5 ____ 5 ____ 5 ____ ns tOW(2) Output Active from End-of-Write 4 ____ 4 ____ 4 ____ 4 ____ ns 2967 tbl 13 |
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