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ADS1625 Datasheet(PDF) 9 Page - Texas Instruments |
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ADS1625 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 37 page  ADS1625 ADS1626 SBAS280E − JUNE 2003 − REVISED MAY 2007 www.ti.com 9 CLK RESET DRDY DOUT[17:0] t 10 t 9 t 12 t 3 t 11 Settled Data NOTE: CS and RD tied low. Figure 3. Reset Timing (ADS1625, ADS1626 with FIFO Disabled) TIMING REQUIREMENTS FOR FIGURE 3 SYMBOL DESCRIPTION MIN TYP MAX UNIT t3 Rising edge of CLK to DRDY low 10 ns t9 RESET pulse width 50 ns t10 Delay from RESET active (low) to DRDY forced high and DOUT forced low 9 ns t11 RESET rising edge to falling edge of CLK −5 10 ns t12 Delay from DOUT active to valid DOUT (settling to 0.001%) 46 DRDY Cycles NOTE: DOUT[17:0] and DRDY load = 10pF. |
Similar Part No. - ADS1625 |
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