ICS8344AYI-01LF datasheet(8/13 Pages) IDT

Part #	ICS8344AYI-01LF

Description	LOW SKEW, 1-TO-24 DIFFERENTIAL -TO-LVCMOS/LVTTL FANOUT BUFFER

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Manufacturer	IDT [Integrated Device Technology]

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IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

8

ICS8344AYI-01 REV. B MAY 10, 2007

ICS8344I-01

LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

PRELIMINARY

APPLICATION INFORMATION

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

DD

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V

DD

= 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

V_REF

R1

1K

C1

0.1u

R2

1K

Single Ended Clock Input

CLKx

nCLKx

VDD

INPUTS:

CLK/nCLK INPUT:

For applications not requiring the use of the differential input,

both CLK and nCLK can be left floating. Though not required, but

for additional protection, a 1k

Ω resistor can be tied from CLK to

ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k

Ω resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating. There should be

no trace attached.

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ICS8344AYI-01LF Datasheet(PDF) 8 Page - Integrated Device Technology

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