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P4C116-15PMB Datasheet(PDF) 6 Page - Pyramid Semiconductor Corporation |
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P4C116-15PMB Datasheet(HTML) 6 Page - Pyramid Semiconductor Corporation |
6 / 14 page P4C116/P4C116L Page 6 of 14 Document # SRAM110 REV A Mode CE CE CE CE CE OE OE OE OE OE WE WE WE WE WE I/O Power Standby H X X High Z Standby D OUT Disabled L H H High Z Active Read L L H D OUT Active Write L X L High Z Active Input Pulse Levels GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and 2 AC TEST CONDITIONS TRUTH TABLE Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C116/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50 Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116 Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). |
Similar Part No. - P4C116-15PMB |
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Similar Description - P4C116-15PMB |
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