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P4C1024L55TI Datasheet(PDF) 5 Page - Pyramid Semiconductor Corporation |
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P4C1024L55TI Datasheet(HTML) 5 Page - Pyramid Semiconductor Corporation |
5 / 11 page P4C1024L Page 5 of 10 Document # SRAM125 REV C -55 Notes: 6. CE 1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE 1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) WRITE CYCLE NO. 1 (WE WE WE WE WE CONTROLLED)(6) Symbol Parameter Max -70 Max Unit Min Min t WC t CW t AS t WP t AH t DH t WZ t OW Write Cycle Time 55 70 ns Chip Enable Time to End of Write 50 60 ns Address Valid to End of Write 50 60 ns Address Set-up Time 00 ns Write Pulse Width 40 50 ns Address Hold Time 00 ns Data Valid to End of Write 25 30 ns Data Hold Time 00 ns Write Enable to Output in High Z 25 30 ns Output Active from End of Write 55 ns t AW t DW |
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