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P4C1026-25L32C Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C1026-25L32C Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 10 page 1 Document # SRAM127 REV E Revised April 2007 DESCRIPTION The P4C1026 is a 1 Meg ultra high speed static RAM organizedas256Kx4.TheCMOSmemoryrequiresnoclock or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V±10% tolerance power supply. With battery backup,dataintegrityismaintainedforsupplyvoltagesdown to 2.0V. TTL/CMOS Compatible Outputs Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 28-Pin 300 mil SOJ – 28-Pin 400 mil SOJ – 28-Pin 400 mil Ceramic DIP – 32-Pin Ceramic LCC FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 15/20/25/35 ns (Commercial/Industrial) – 20/25/35 ns (Military) Low Power Single 5V±10% Power Supply Data Retention with 2.0V Supply Three-State Outputs FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM SOJ (J5, J7), DIP (C7) Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system speeds. CMOS is utilized to reduce power consumption. TheP4C1026is availableina28-pin300miland400milSOJ packages, as well as Ceramic DIP and LCC packages, providing excellent board level densities. LCC(L13) |
Similar Part No. - P4C1026-25L32C |
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