P4C1023L-55CMB datasheet(1/11 Pages) PYRAMID

Part #	P4C1023L-55CMB

Description	LOW POWER 128K x 8 SINGLE CHIP ENABLE CMOS STATIC RAM

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Manufacturer	PYRAMID [Pyramid Semiconductor Corporation]

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Document # SRAM126 REV OR

Revised October 2005

P4C1023/P4C1023L

LOW POWER 128K x 8

SINGLE CHIP ENABLE

CMOS STATIC RAM

locations are specified on address pins A

0 to A16. Read-

ing is accomplished by device selection (CE low) and

output enabling (OE) while write enable (WE) remains

HIGH. By presenting the address under these condi-

tions, the data in the addressed memory location is pre-

sented on the data input/output pins. The input/output

pins stay in the HIGH Z state when either CE is HIGH or

WE is LOW.

The P4C1023L is packaged in a 32-pin 400 or 600 mil

ceramic DIP and in a 32-pin ceramic SOJ.

The P4C1023L is a 1 Megabit low power CMOS static

RAM organized as 128K x 8. The CMOS memory re-

quires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 55 ns and 70 ns are availale. CMOS is

utilized to reduce power consumption to a low level.

The P4C1023L device provides asynchronous opera-

tion with matching access and cycle times. Memory

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—32-Pin 400 or 600 mil Ceramic DIP

—32-Pin Ceramic SOJ

V

CC Current

— Operating: 35mA

— CMOS Standby: 100µA

Access Times

—55/70 ns

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using CE

CE

CE and OE

OE

Inputs

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (C10, C11), CERAMIC SOJ (CJ1)

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