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P4C1048L-45PMB Datasheet(PDF) 7 Page - Pyramid Semiconductor Corporation |
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P4C1048L-45PMB Datasheet(HTML) 7 Page - Pyramid Semiconductor Corporation |
7 / 12 page P4C1048L Page 7 of 12 Document # SRAM129 REV D Write Active Read TIMING WAVEFORM OF WRITE CYCLE NO.2 ( CE CE CE CE CE CONTROLLED)(6) * including scope and test fixture. Note: Because of the high speed of the P4C1048L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between V CC and ground. To avoid signal reflections, proper termination must be used; for example, a 50 Ω test environment should be terminated into a 50Ω load with 1.77V (Thevenin Voltage) at the comparator input, and a 589 Ω resistor must be used in series with D OUT to match 639Ω (Thevenin Resistance). AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Fig. 1 and 2 Mode Standby D OUT Disabled Standby Power I/O WE WE WE WE WE OE OE OE OE OE CE CE CE CE CE High Z D OUT D IN X H H L X H L X H L L L Active Active High Z Figure 1. Output Load Figure 2. Thevenin Equivalent |
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