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IDT70125S55JG Datasheet(PDF) 10 Page - Integrated Device Technology

Part # IDT70125S55JG
Description  HIGH-SPEED 2K x 9 DUAL-PORT STATIC RAM WITH BUSY & INTERRUPT
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT70125S55JG Datasheet(HTML) 10 Page - Integrated Device Technology

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6.42
IDT70121/IDT70125
High-Speed 2K x 9 Dual-Port Static RAM with Busy & Interrupt
Industrial and Commercial Temperature Ranges
10
APRIL 05, 2006
AC Electrical Characteristics Over the Operating Temperature
and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and
BUSY.
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'..
5. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
6. 'X' in part numbers indicates power rating (S or L).
70121X25
70125X25
Com'l Only
70121X35
70125X35
Com'l
& Ind
Symbol
Parameter
Min.Max.Min.Max.
Unit
BUSY TIMING (For MASTER IDT70121)
tBAA
BUSY Access Time from Address
____
20
____
20
ns
tBDA
BUSY Disable Time from Address
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
ns
tWDD
Write Pulse to Data Delay(1)
50
60
tDDD
Write Data Valid to Read Data Delay(1)
35
45
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
30
____
30
ns
tWH
Write Hold After
BUSY(5)
15
____
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT70125)
tWB
Write to
BUSY Input(4)
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
15
____
20
____
ns
tWDD
Write Pulse to Data Delay(1)
____
50
____
60
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
35
____
45
ns
2654 tbl 11a
70121X45
70125X45
Com'l Only
70121X55
70125X55
Com'l Only
Symbol
Parameter
Min.Max.Min.Max.
Unit
BUSY TIMING (For MASTER IDT 70121)
tBAA
BUSY Access Time from Address
____
20
____
30
ns
tBDA
BUSY Disable Time from Address
____
20
____
30
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
30
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
30
ns
tWDD
Write Pulse to Data Delay(1)
70
80
tDDD
Write Data Valid to Read Data Delay(1)
55
65
tAPS
Arbitration Priority Set-up Time(2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
35
____
45
ns
tWH
Write Hold After
BUSY(5)
20
____
20
____
ns
BUSY INPUT TIMING (For SLAVE IDT 70125)
tWB
Write to
BUSY Input(4)
0
____
0
____
ns
tWH
Write Hold After
BUSY(5)
20
____
20
____
ns
tWDD
Write Pulse to Data Delay(1)
____
70
____
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
55
____
65
ns
2654 tbl 11b


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