9

COMMERCIALTEMPERATURERANGE

IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO

512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9

JULY 17, 2006

TABLE II—RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs

Internal Status

Outputs

Mode

RS

FL

XI

Read Pointer

Write Pointer

EF

FF

Reset First Device

0

0

(1)

LocationZero

LocationZero

0

1

Reset All Other Devices

0

1

(1)

LocationZero

LocationZero

0

1

Read/Write

1

X

(1)

X

X

X

X

NOTE:

1.

XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

XI = Expan-

sion Input,

HF = Half-Full Flag Output

TABLE I—RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs

Internal Status

Outputs

Mode

RS

RT

XI

Read Pointer

Write Pointer

EF

FF

HF

Reset

0

X

0

LocationZero

LocationZero

0

1

1

Retransmit

1

0

0

LocationZero

Unchanged

X

X

X

Read/Write

1

1

0

Increment

(1)

Increment

(1)

XXX

NOTE:

1. Pointer will increment if flag is High.

Figure 14. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 and 32,768 x 9 FIFO Memory (Depth Expansion)

D

W

FFB

EFB

FLB

XOB

RSA

FULL

EMPTY

R

9

9

99

XIB

9

Q

FFA

EFA

FLA

XOA

XIA

FFB

EFB

FLB

XIB

3966 drw 16

XOA

FIFO A

FIFO B

FIFO A

FIFO B

XIA

XOB

EFA

FLA

FFA

72V81/72V82

72V83/72V84

72V85

72V81/72V82

72V83/72V84

72V85