INDUSTRIALTEMPERATURERANGE

2

IDT74FCT823AT/CT

HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER

PIN CONFIGURATION

Symbol

Description

Max

Unit

Terminal Voltage with Respect to GND

–0.5 to +7

V

Terminal Voltage with Respect to GND

V

Storage Temperature

–65 to +150

° C

DC Output Current

–60 to +120

mA

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability. No terminal voltage may exceed

Vcc by +0.5V unless otherwise noted.

2. Inputs and Vcc terminals only.

3. Output and I/O terminals only.

Symbol

Parameter

(1)

Conditions

Typ.

Max.

Unit

Input Capacitance

6

10

pF

Output Capacitance

8

12

pF

NOTE:

1. This parameter is measured at characterization but not tested.

Internal/

Inputs

Outputs

OE

CLR

EN

Dx

CP

Qx

Yx

Function

HHL

L

↑

L

Z

High Z

HHL

H

↑

HZ

H

L

X

X

X

L

Z

Clear

LL

X

X

X

L

L

H

H

H

X

X

N C

Z

Hold

LH

HX

X

N C

N C

HHL

L

↑

L

Z

Load

HHL

H

↑

HZ

LH

L

L

↑

LL

LH

L

H

↑

HH

NOTE:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

NC = No Change

↑ = LOW-to-HIGH Transition

Z = High Impedance

2

3

1

20

19

18

15

16

9

10

23

22

24

21

17

5

6

7

4

8

CP

OE

13

14

11

12

GND

CLR

EN

SOIC/ QSOP

TOP VIEW

Pin Names

I/O

Description

Dx

I

D Flip-Flop Data Inputs

CLR

I

When the clear input is LOW and

OE is LOW, the

Qx outputs are LOW. When the clear input is HIGH,

data can be entered into the register.

C P

I

Clock Pulse for the Register; enters data into the

register on the LOW-to-HIGH transition.

Y x

O

Register 3-State Outputs

EN

I

Clock Enable. When the clock enable is LOW, data

on the Dx output is transferred to the Qx output on the

LOW-to-HIGH transition. When the clock enable is

HIGH, the Qx outputs do not change state, regardless

of the data or clock input transitions.

OE

I

Output Control. When the

OE is HIGH, the Yx

outputs are in the high-impedance state. When the

OE is LOW, the TRUE register data is present at the

Yx outputs.

PIN DESCRIPTION