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P4C167L-12JMB Datasheet(PDF) 1 Page - Pyramid Semiconductor Corporation |
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P4C167L-12JMB Datasheet(HTML) 1 Page - Pyramid Semiconductor Corporation |
1 / 10 page 1 Document # SRAM106 REV A Revised October 2005 FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 12/15/20/25/35 ns (Industrial) – 15/20/25/35/45 ns (Military) Low Power Operation Single 5V±10% Power Supply Data Retention with 2.0V Supply (P4C167L Military) P4C167/P4C167L ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM DIP (P2, C6) SOJ (J2) SIMILAR Separate Data I/O Three-State Output TTL Compatible Output Fully TTL Compatible Inputs Standard Pinout (JEDEC Approved) – 20-Pin 300 mil DIP – 20-Pin 300 mil SOJ – 20-Pin LCC DESCRIPTION The P4C167/L are 16,384-bit high speed static RAMs or- ganizedas16Kx1.TheCMOSmemoriesrequirenoclocks or refreshing and have equal access and cycle times. The RAMs operate from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 10µA. Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. CMOS reduces power consumption to low levels. The P4C167/L are available in 20-pin 300 mil DIP, 20-pin 300 mil SOJ, and 20-pin LCC packages providing excel- lent board level densities. 1 LCC (L9) |
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