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IDT72265LA Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72265LA Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 27 page 9 IDT72255LA/72265LA CMOS SuperSync FIFO™ 8,192 x 18 and 16,384 x 18 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 17, 2005 Figure 4. Programmable Flag Offset Programming Sequence NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes. Figure 3. Offset Register Location and Default Values EMPTY OFFSET REGISTER 17 0 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset FULL OFFSET REGISTER 17 0 DEFAULT VALUE DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset 12 12 72255LA — 8,192 x 18–BIT 4670 drw06 EMPTY OFFSET REGISTER 17 0 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset FULL OFFSET REGISTER 17 0 DEFAULT VALUE DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset 13 13 72265LA — 16,384 x 18–BIT Selection Parallel write to registers: Empty Offset Full Offset Parallel read from registers: Empty Offset Full Offset No Operation Write Memory Read Memory No Operation 4670 drw07 LD 0 0 X 1 1 1 0 WEN 0 1 1 0 X 1 1 REN 1 0 1 X 0 1 1 Serial shift into registers: 26 bits for the 72255LA 28 bits for the 72265LA SEN 1 1 1 X X X 0 WCLK X X X X RCLK X X X X X 1 bit for each rising WCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) |
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