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COMMERCIALTEMPERATURERANGE

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

FEBRUARY 10, 2006

WCLK

WEN

RCLK

EF

REN

D0

D1

(first valid write)

(1)

D2

D3

OE

D0

D1

2680 drw 07

NOTE:

1.

EF to change during the current clock cycle. If the time between the rising edge of WCLK and the

EF may not change state until the next RCLK edge.

Figure 4. Read Cycle Timing

Figure 5. First Data Word Latency Timing

NOTE:

1.

The Latency Timing apply only at the Empty Boundary (

EF = LOW).

NO OPERATION

RCLK

REN

EF

VALID DATA

OE

WCLK

(1)

WEN

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