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IDT72240L10TPG Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT72240L10TPG Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 11 page 9 COMMERCIALTEMPERATURERANGE IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™ 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8 FEBRUARY 10, 2006 NOTES: 1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge. 2. If a write is performed on this rising edge of the Write Clock, there will be Full - 6 words in the FIFO when AF goes LOW. Figure 8. Almost Full Flag Timing NOTES: 1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge. 2. If a read is performed on this rising edge of the Read Clock, there will be Empty - 6 words in the FIFO when AE goes LOW. Figure 9. Almost Empty Flag Timing WCLK WEN tENS AE tENH tCLKH tCLKL tAE RCLK REN tENS Empty+7 Empty+8 tSKEW2 (1) tENH (2) tAE 2680 drw 11 WCLK WEN tENS AF tENH tCLKH tCLKL RCLK REN tENS tSKEW2 (1) Full - 8 words in FIFO Full - 7 words in FIFO (2) tAF tAF tENH 2680 drw10 |
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