9

COMMERCIALTEMPERATURERANGE

IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™

64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8

FEBRUARY 10, 2006

NOTES:

1.

AF to change during the current clock cycle. If the time between the rising edge of RCLK and the

AF may not change state until the next WCLK edge.

2.

If a write is performed on this rising edge of the Write Clock, there will be Full - 6 words in the FIFO when

AF goes LOW.

Figure 8. Almost Full Flag Timing

NOTES:

1.

AE to change during the current clock cycle. If the time between the rising edge of WCLK and the

AE may not change state until the next RCLK edge.

2.

If a read is performed on this rising edge of the Read Clock, there will be Empty - 6 words in the FIFO when

AE goes LOW.

Figure 9. Almost Empty Flag Timing

WCLK

WEN

AE

RCLK

REN

Empty+7

Empty+8

(1)

(2)

2680 drw 11

WCLK

WEN

AF

RCLK

REN

(1)

Full - 8 words in FIFO

Full - 7 words in FIFO

(2)

2680 drw10