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LB11873 Datasheet(PDF) 9 Page - Sanyo Semicon Device |
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LB11873 Datasheet(HTML) 9 Page - Sanyo Semicon Device |
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9 / 14 page  LB11873 No.A0081-9/14 Continued from preceding page. Pin No. Pin Description Equivalent Circuit 18 CSD Initial reset pulse generation and protection circuit reference oscillator Connect a capacitor between this pin and ground. 19 FGS FG Schmitt trigger output 20 LD Phase lock detection output This output goes to the on state (low-level output) in the phase locked state. 21 S/S Start/stop control Low : 0V to 1.0V High : 2.0V to VREG Hysteresis : about 0.25V This pin goes to the high level when open. A low level specifies the start state. 22 CLK Clock input Low : 0V to 1.0V High : 2.0V to VREG Hysteresis : about 0.25V fCLK = 10kHz max. If there is noise on this signal, insert a noise rejection capacitor at this input. Continued on next page. VREG 300 Ω 18 19 20 5k Ω VREG VREG 5k Ω 21 VREG 20k Ω 30k Ω VREG 20k Ω 22 30k Ω |
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