MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS12018-A

FLAT-BASE TYPE

INSULATED TYPE

Jan. 2000

PRELIMINARY

Notice:

This

is not

a final

specification.

Some

parametric

limits

are subject

to change.

Gate signal Vo of each phase

upper arm(ASIPM internal)

upper arm

0V

0V

0V

0V

0V

0V

0V

0V

0V

(ASIPM internal)

(ASIPM internal)

200

–200

Analogue output signal

data hold range

1

2

3

4

5

400

300

100

0

–100

–300

–400

0

min

max

Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-

neously in “LOW” level.

whichever comes in later.

gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING

LINEARITY

Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING

“DATA HOLD” DEFINITION

Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART

0V

500

µs

Note ; Ringing happens around the point where the signal output

voltage changes state from “analogue” to “data hold” due

to test circuit arrangement and instrumentational trouble.

Therefore, the rate of change is measured at a 5

µs delayed point.