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AN1759 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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AN1759 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
7 / 24 page Application Note DS1307 Hardware Interface AN1759 7 Figure 4. Start and Stop Transfer Timing Data Transfer Data is transmitted on the rising edge of SCL. Data can only be changed while SCL is LOW. The receiving device samples the bus after SCL goes HIGH. There is one clock pulse per bit of data transmitted. See Figure 5. Figure 5. Data Transfer Timing Acknowledge Transfer The acknowledge transfer is a type of handshaking convention used to signify that a successful transfer of data has taken place. After the transmitting device sends out the eighth bit of a byte of data, it releases the bus. The master sends out a ninth clock signal and the receiver acknowledges the transfer by pulling SDA LOW. Once the transmitter reads the LOW condition of SDA, it proceeds by taking over the bus and sending out the next byte of data. If the DS1307 is transmitting data and the master wants to end further transmissions, the master sends a NO ACK signal (HIGH) back to the DS1307. This tells the DS1307 that no more transfers are needed and the stop transfer condition will be initiated soon. See Figure 6 for these different timing patterns. SCL SDA START STOP SCL SDA DATA CHANGE DATA STABLE DATA STABLE Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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