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C8051F410-GQ Datasheet(PDF) 11 Page - Silicon Laboratories |
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C8051F410-GQ Datasheet(HTML) 11 Page - Silicon Laboratories |
11 / 270 page Rev. 1.0 11 C8051F410/1/2/3 23. Enhanced Serial Peripheral Interface (SPI0) Figure 23.1. SPI Block Diagram ............................................................................. 217 Figure 23.2. Multiple-Master Mode Connection Diagram ....................................... 220 Figure 23.3. 3-Wire Single Master and Slave Mode Connection Diagram ............. 220 Figure 23.4. 4-Wire Single Master and Slave Mode Connection Diagram ............. 220 Figure 23.5. Data/Clock Timing Relationship ......................................................... 222 Figure 23.6. SPI Master Timing (CKPHA = 0) ........................................................ 227 Figure 23.7. SPI Master Timing (CKPHA = 1) ........................................................ 227 Figure 23.8. SPI Slave Timing (CKPHA = 0) .......................................................... 228 Figure 23.9. SPI Slave Timing (CKPHA = 1) .......................................................... 228 24. Timers Figure 24.1. T0 Mode 0 Block Diagram.................................................................. 232 Figure 24.2. T0 Mode 2 Block Diagram.................................................................. 233 Figure 24.3. T0 Mode 3 Block Diagram.................................................................. 234 Figure 24.4. Timer 2 16-Bit Mode Block Diagram .................................................. 239 Figure 24.5. Timer 2 8-Bit Mode Block Diagram .................................................... 240 Figure 24.6. Timer 2 Capture Mode Block Diagram ............................................... 241 Figure 24.7. Timer 3 16-Bit Mode Block Diagram .................................................. 244 Figure 24.8. Timer 3 8-Bit Mode Block Diagram .................................................... 245 Figure 24.9. Timer 3 Capture Mode Block Diagram ............................................... 246 25. Programmable Counter Array (PCA0) Figure 25.1. PCA Block Diagram............................................................................ 249 Figure 25.2. PCA Counter/Timer Block Diagram.................................................... 250 Figure 25.3. PCA Interrupt Block Diagram ............................................................. 251 Figure 25.4. PCA Capture Mode Diagram.............................................................. 252 Figure 25.5. PCA Software Timer Mode Diagram .................................................. 253 Figure 25.6. PCA High-Speed Output Mode Diagram............................................ 254 Figure 25.7. PCA Frequency Output Mode ............................................................ 255 Figure 25.8. PCA 8-Bit PWM Mode Diagram ......................................................... 256 Figure 25.9. PCA 16-Bit PWM Mode...................................................................... 257 Figure 25.10. PCA Module 5 with Watchdog Timer Enabled ................................. 258 26. C2 Interface Figure 26.1. Typical C2 Pin Sharing....................................................................... 267 |
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