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C8051F364-GQ1 Datasheet(PDF) 9 Page - Silicon Laboratories |
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C8051F364-GQ1 Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 288 page  Rev. 1.0 9 C8051F360/1/2/3/4/5/6/7/8/9 Figure 8.2. Comparator1 Functional Block Diagram ............................................... 71 Figure 8.3. Comparator Hysteresis Plot .................................................................. 72 9. CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram .......................................................................... 81 Figure 9.2. Memory Map ......................................................................................... 86 Figure 9.3. SFR Page Stack .................................................................................... 89 Figure 9.4. SFR Page Stack While Using SFR Page 0x0F To Access OSCICN .... 90 Figure 9.5. SFR Page Stack After ADC0 Window Comparator Interrupt Occurs .... 91 Figure 9.6. SFR Page Stack Upon PCA Interrupt Occurring During an ADC0 ISR . 91 Figure 9.7. SFR Page Stack Upon Return From PCA Interrupt .............................. 92 Figure 9.8. SFR Page Stack Upon Return From ADC2 Window Interrupt .............. 93 10. Interrupt Handler 11. Multiply And Accumulate (MAC0) Figure 11.1. MAC0 Block Diagram ........................................................................ 117 Figure 11.2. Integer Mode Data Representation ................................................... 118 Figure 11.3. Fractional Mode Data Representation ............................................... 118 Figure 11.4. MAC0 Pipeline ................................................................................... 119 12. Reset Sources Figure 12.1. Reset Sources ................................................................................... 128 Figure 12.2. Power-On and VDD Monitor Reset Timing ....................................... 129 13. Flash Memory Figure 13.1. Flash Program Memory Map ............................................................. 138 14. Branch Target Cache Figure 14.1. Branch Target Cache Data Flow ....................................................... 145 Figure 14.2. Branch Target Cache Organization ................................................... 146 Figure 14.3. Cache Lock Operation ....................................................................... 148 15. External Data Memory Interface and On-Chip XRAM Figure 15.1. Multiplexed Configuration Example ................................................... 157 Figure 15.2. Non-multiplexed Configuration Example ........................................... 158 Figure 15.3. EMIF Operating Modes ..................................................................... 159 Figure 15.4. Non-multiplexed 16-bit MOVX Timing ............................................... 162 Figure 15.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 163 Figure 15.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 164 Figure 15.7. Multiplexed 16-bit MOVX Timing ....................................................... 165 Figure 15.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 166 Figure 15.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 167 16. Oscillators Figure 16.1. Oscillator Diagram ............................................................................. 169 Figure 16.2. 32.768 kHz External Crystal Example ............................................... 176 Figure 16.3. PLL Block Diagram ............................................................................ 178 17. Port Input/Output Figure 17.1. Port I/O Functional Block Diagram (Port 0 through Port 3) ............... 183 Figure 17.2. Port I/O Cell Block Diagram .............................................................. 184 Figure 17.3. Crossbar Priority Decoder with No Pins Skipped .............................. 185 Figure 17.4. Crossbar Priority Decoder with Port Pins Skipped ............................ 186 |
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