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SI5017-X-GM Datasheet(PDF) 8 Page - Silicon Laboratories |
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SI5017-X-GM Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 26 page Si5017 8 Rev. 1.4 Table 3. AC Characteristics (Clock and Data) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Clock Rate fCLK 2.4 — 2.7 GHz Output Clock Rise Time tR Figure 3 — 70 90 ps Output Clock Fall Time tF Figure 3 — 70 90 ps Output Clock Duty Cycle 48 50 52 % of UI Output Data Rise Time tR Figure 3 — 80 110 ps Output Data Fall Time tF Figure 3 — 80 110 ps Clock to Data Delay FEC (2.7 Gbps) OC-48 tCr-D Figure 2 190 190 230 230 265 265 ps Clock to Data Delay FEC (2.7 Gbps) OC-48 tCf-D Figure 2 –70 –60 –40 –30 –10 0 ps Input Return Loss 100 kHz–1.5 GHz 1.5 GHz–4.0 GHz –15 –10 — — — — dB dB Slicing Level Offset (relative to the internally set input common mode voltage) VSLICE SLICE_LVL = 750 mV to 2.25 V See Figure 8 on page 14. Loss-of-Signal Range* (peak-to-peak differential) VLOS LOS_LVL = 1.50 to 2.50 V 0 — 40 mV Loss-of-Signal Response Time tLOS Figure 5 8 20 25 µs *Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL – 1.50)/25. |
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