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SI5023 Datasheet(PDF) 8 Page - Silicon Laboratories |
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SI5023 Datasheet(HTML) 8 Page - Silicon Laboratories |
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8 / 28 page  Si5023 8 Rev. 1.25 Table 3. AC Characteristics (Clock and Data) (VDD = 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Clock Rate fCLK RATESEL[0:1] = 11 2.46 — 2.7 GHz RATESEL[0:1] = 01 1.232 — 1.35 GHz RATESEL[0:1] = 10 616 — 675 MHz RATESEL[0:1] = 00 154 — 158 MHz Output Clock Rise Time—OC-48 tR Figure 3 on page 6 — 70 90 ps Output Clock Fall Time—OC-48 tF Figure 3 on page 6 — 70 90 ps Output Clock Duty Cycle OC-48/12/3 47 50 53 % of UI Output Data Rise Time—OC-48 tR Figure 3 on page 6 — 80 110 ps Output Data Fall Time—OC-48 tF Figure 3 on page 6 — 80 110 ps Clock-to-Data Delay FEC (2.7 GHz) OC-48 GbE OC-12 OC-3 tCr-D Figure 2 on page 5 190 190 440 800 4000 230 230 490 860 4100 265 265 560 940 4200 ps Clock to Data Delay FEC (2.7 GHz) OC-48 tCf-D Figure 2 on page 5 –70 –60 –40 –30 –10 0 ps Input Return Loss 100 kHz–1.5 GHz 1.5 GHz–4.0 GHz –15 –10 — — — — dB dB Slicing Level Offset (relative to the internally set input common mode voltage) VSLICE SLICE_LVL = 750 mV to 2.25 V See Figures 12 and 13. Loss-of-Signal Range* (peak-to-peak differential) VLOS LOS_LVL = 1.50 TO 2.50 V 0— 40 mV Loss-of-Signal Response Time tLOS Figure 5 on page 6 820 25 µs *Note: Adjustment voltage is calculated as follows: VLOS = (LOS_LVL – 1.50)/25. |
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