SI5310 datasheet(1/26 Pages) SILABS

Part #	SI5310

Description	PRECISION CLOCK MULTIPLIER/REGENERATOR IC

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Manufacturer	SILABS [Silicon Laboratories]

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Rev. 1.2 8/06

Si5310

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Features

Complete precision clock multiplier and clock regenerator device:

Applications

Description

The Si5310 is a fully integrated low-power clock multiplier and clock

regenerator IC. The clock multiplier generates an output clock that is an

integer multiple of the input clock. The clock regenerator operates

simultaneously, creating a “clean” version of the input clock by using the

clock synthesis phase-locked loop (PLL) to remove unwanted jitter and

square up the input clock’s rising and falling edges. The Si5310 uses

Silicon Laboratories patented DSPLL® architecture to achieve superior

jitter performance while eliminating the analog loop filter found in

traditional PLL designs with a digital signal-processing algorithm.

The Si5310 represents a new standard in low jitter, small size, low power,

and ease-of-use for clock devices. It operates from a single 2.5 V supply

over the industrial temperature range (–40 to 85 °C).

Functional Block Diagram

Performs clock multiplication to one

of two frequency ranges:

150–167 MHz or 600–668 MHz

Jitter generation as low as

0.5 psrms for 622 MHz output

Accepts input clock from

9.4–668 MHz

Regenerates a “clean”, jitter-

attenuated version of input clock

DSPLL™ technology provides

superior jitter performance

Small footprint: 4 x 4 mm

Low power: 310 mW typical

ROHS-compliant Pb-free

packaging option available

SONET/SDH systems

Terabit routers

Digital cross connects

Optical transceiver modules

Gigabit Ethernet systems

Fibre channel

DSPLL®

Phase-Locked

Loop

BUF

CLKIN+

CLKIN–

2

MULTSEL

REFCLK+

REFCLK–

2

LOL

MULTOUT+

MULTOUT–

CLKOUT+

CLKOUT–

Bias Gen

REXT

BUF

Calibration

Regeneration

PWRDN/CAL

Ordering Information:

See page 21.

Pin Assignments

Si5310

GND

Pad

15

14

13

12

11

PWRDN

CLKOUT+

VDD

CLKOUT–

VDD

1

2

3

4

5

VDD

GND

REFCLK–

REXT

REFCLK+

20 19 18 17 16

6

7

8

9

10

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