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SI5310-BM Datasheet(PDF) 9 Page - Silicon Laboratories |
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SI5310-BM Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 26 page  Si5310 Rev. 1.2 9 Jitter Transfer Bandwidth (MULTSEL = 1, MULTOUT = 150 to 167 MHz)* JBW Clock Input (MHz) = 9.375 to 10.438 —19 26 kHz Clock Input (MHz) = 18.750 to 20.875 —38 53 kHz Clock Input (MHz) = 37.500 to 41.750 — 75 105 kHz Clock Input (MHz) = 75.000 to 83.500 — 150 210 kHz Clock Input (MHz) = 150.000 to 167.000 — 300 420 kHz Jitter Transfer Peaking (MULTSEL = 0, MULTOUT = 600 to 668 MHz)* JP Clock Input (MHz) = 37.500 to 41.750 — 0.12 0.4 dB Clock Input (MHz) = 75.000 to 83.500 — 0.06 0.2 dB Clock Input (MHz) = 150.000 to 167.000 — 0.03 0.1 dB Clock Input (MHz) = 300.000 to 334.000 — 0.02 0.066 dB Clock Input (MHz) = 600.000 to 668.000 — 0.01 0.033 dB Jitter Transfer Peaking (MULTSEL = 1, MULTOUT = 150 to 167 MHz)* JP Clock Input (MHz) = 9.375 to 10.438 — 0.12 0.4 dB Clock Input (MHz) = 18.750 to 20.875 — 0.06 0.2 dB Clock Input (MHz) = 37.500 to 41.750 — 0.03 0.1 dB Clock Input (MHz) = 75.000 to 83.500 — 0.02 0.066 dB Clock Input (MHz) = 150.000 to 167.000 — 0.01 0.033 dB Acquisition Time TAQ After falling edge of PWRDN/CAL 1.45 1.5 1.7 ms From the return of valid CLKIN 40 60 150 µs Frequency Difference at which PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL 450 600 750 ppm Frequency Difference at which PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK 150 300 450 ppm Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD = 2.5 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit *Note: See PLL Performance section of this document for test descriptions. |
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