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SI5367A-B-GQ Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5367A-B-GQ Datasheet(HTML) 1 Page - Silicon Laboratories |
1 / 18 page Preliminary Rev. 0.3 3/07 Copyright © 2007 by Silicon Laboratories Si5367 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5367 µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER Description The Si5367 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5367 accepts four clock inputs ranging from 10 to 707 MHz and generates five frequency-multiplied clock outputs ranging from 10 to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5367 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5367 is based on Silicon Laboratories' 3rd- generation DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5 V supply, the Si5367 is ideal for providing clock multiplication in high performance timing applications. Applications SONET/SDH OC-48/OC-192 line cards GbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 and custom FEC line cards Wireless basestations Data converter clocking xDSL SONET/SDH + PDH clock synthesis Test and measurement Features Generates any frequency from 10 to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 10 to 710 MHz Low jitter clock outputs w/jitter generation as low as 0.6 ps rms (50 kHz–80 MHz) Integrated loop filter with selectable loop bandwidth (30 kHz to 1.3 MHz) Four clock inputs w/manual or automatically controlled hitless switching Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable settings On-chip voltage regulator for 1.8 or 2.5 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant PRELIMINARY DATA SHEET I2C/SPI Port Clock Select CKOUT2 CKIN1 CKOUT1 CKIN2 Control ÷ NC1 ÷ NC2 CKIN3 CKIN4 CKOUT4 ÷ NC4 CKOUT5 ÷ NC5 VDD (1.8 or 2.5 V) GND ÷ N32 ÷ N31 DSPLL ® ÷ N2 CKOUT3 ÷ NC3 ÷ N33 ÷ N34 Device Interrupt LOS Alarms |
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